A wafer-level three-dimensional integration scheme with Cu TSVs based on microbump/adhesive hybrid bonding for three-dimensional memory application

Cheng Ta Ko*, Zhi Cheng Hsiao, Yao Jen Chang, Peng Shu Chen, Yu Jiau Hwang, Huan Chun Fu, Jui Hsiung Huang, Chia Wen Chiang, Shyh Shyuan Sheu, Yu Hua Chen, Wei Chung Lo, Kuan-Neng Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

15 Scopus citations

Abstract

Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.

Original languageEnglish
Article number6186810
Pages (from-to)209-216
Number of pages8
JournalIEEE Transactions on Device and Materials Reliability
Volume12
Issue number2
DOIs
StatePublished - 14 Jun 2012

Keywords

  • 3-D IC
  • 3-D integration
  • Hybrid bonding
  • wafer level

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