A W-band current combined power amplifier with 14.8dBm Psat and 9.4% maximum PAE in 65nm CMOS

Zhiwei Xu*, Qun Jane Gu, Mau-Chung Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

We present a 101-117GHz power amplifier (PA) using two way current power combiner in 65nm bulk CMOS. It delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. To ensure the stability and improve efficiency, the PA first two stages adopt cascode structure and the last stage utilizes common source structure. A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.

Original languageEnglish
Title of host publication2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers
DOIs
StatePublished - 1 Aug 2011
Event2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Baltimore, MD, United States
Duration: 5 Jun 20117 Jun 2011

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Conference

Conference2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011
CountryUnited States
CityBaltimore, MD
Period5/06/117/06/11

Keywords

  • Adaptive Bias
  • CMOS
  • PAE
  • Power Amplifier
  • Power Combiner
  • Saturated Output Power
  • W-band

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    Xu, Z., Gu, Q. J., & Chang, M-C. (2011). A W-band current combined power amplifier with 14.8dBm Psat and 9.4% maximum PAE in 65nm CMOS. In 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers [5940619] (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2011.5940619