A silicon-on-insulator, fully-complementary BiCMOS process has been developed for realizing high-performance circuit operation in the sub-3.3 V power supply regime. Complementary, double-diffused lateral BJTs and fully-overlapped, asymmetrical DDD MOSFETs have been successfully integrated in a 10-mask process by utilizing the process simplifications that are unique to thin-film SOI substrates. The BJTs exhibit the highest lateral current gains reported to date, with hfe=120 and 225 for the NPN and PNP, respectively. NPN ft=4.5 GHz was achieved, and ft>20 GHz is possible with an improved layout. The MOSFETs demonstrate excellent short-channel behavior down to Leff=0.18 mu m, with Tox=10 nm. The p+ gate, SOI PMOS device exhibits superior Idsat and gmsat. A record propagation delay of 12 ps/stage at Vdd=5 V and 300 K was obtained for the CMOS ring oscillators fabricated in this technology. This demonstrates the performance achievable with a deep-submicron SOI process.