A verification-aware design methodology for thread pipelining parallelization

Guo An Jian*, Cheng An Chien, Peng Sheng Chen, Jiun-In Guo

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

This paper proposes a verification-aware design methodology that provides developers with a systematic and reliable approach to performing thread-pipelining parallelization on sequential programs. In contrast to traditional design flow, a behavior-model program is constructed before parallelizing as a bridge to help developers gradually leverage the technique of thread-pipelining parallelization. The proposed methodology integrates verification mechanisms into the design flow. To demonstrate the practicality of the proposed methodology, we applied it to the parallelization of a 3D depth map generator with thread pipelining. The parallel 3D depth map generator was further integrated into a 3D video playing system for evaluation of the verification overheads of the proposed methodology and the system performance. The results show the parallel system can achieve 33.72 fps in D1 resolution and 12.22 fps in HD720 resolution through a five-stage pipeline. When verifying the parallel program, the proposed verification approach keeps the performance degradation within 23% and 21.1% in D1 and HD720 resolutions, respectively.

Original languageEnglish
Pages (from-to)2505-2513
Number of pages9
JournalIEICE Transactions on Information and Systems
VolumeE95-D
Issue number10
DOIs
StatePublished - 1 Jan 2012

Keywords

  • 3D depth map generation
  • Behavior model
  • Parallel computing
  • Pipeline
  • Verification

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