A variable partitioning algorithm of BDD for FPGA technology mapping

Jie Hong Jiang*, Jing Yang Jout, Juinn-Dar Huang, Jung Shian Wei

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches [1], [4].

Original languageEnglish
Pages (from-to)1813-1819
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE80-A
Issue number10
StatePublished - 1 Jan 1997

Keywords

  • Binary decision diagrams
  • Equivalent class
  • LUT-based FPGA
  • RothKarp decomposition

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