A variable-gain time amplifier with automatic interval detection

Frank Hsiao, Jung Chin Lai, Terng-Yin Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents an all-digital standard cell SR-Latch based time amplifier (TA) with a variable gain of 6X and 12X. In this TA, a two-stage gain selection unit is applied to enable the TA to select either the high gain for short input pulse intervals or the low gain for long input pulse intervals. The time amplification gain is 6 in the input range of -700ps ∼700ps, and reaches 12 if the input range is -300∼300ps. We present a design that automatically detects the input pulse and switches to the proper TA gain. By applying the proposed TA, a standard cyclic TDC implemented in a UMC CMOS 65-nm process shows the resolution improved from 1.6ps to 0.8 ps.

Original languageEnglish
Title of host publicationISOCC 2015 - International SoC Design Conference
Subtitle of host publicationSoC for Internet of Everything (IoE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages263-264
Number of pages2
ISBN (Electronic)9781467393089
DOIs
StatePublished - 8 Feb 2016
Event12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of
Duration: 2 Nov 20155 Nov 2015

Publication series

NameISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Conference

Conference12th International SoC Design Conference, ISOCC 2015
CountryKorea, Republic of
CityGyeongju
Period2/11/155/11/15

Keywords

  • skew calibration
  • TA
  • TDC

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