A universal VLSI architecture for Reed-Solomon error-and-erasure decoders

Hsie-Chia Chang*, Chein Ching Lin, Fu Ke Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-μm 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm 2 silicon area, and the average core power consumption is 68.1 mW.

Original languageEnglish
Pages (from-to)1960-1967
Number of pages8
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume56
Issue number9
DOIs
StatePublished - 24 Sep 2009

Keywords

  • Error-and-erasure correction
  • Montgomery multiplication
  • Reed-Solomon (RS) code
  • Universal architecture

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