A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step

Wei Ting Lai, Kuo Ching Yang, Ting Chia Hsu, Po Hsiang Liao, Thomas George, Pei Wen Li*

*Corresponding author for this work

Research output: Contribution to journalArticle

8 Scopus citations

Abstract

We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our “designer” heterostructure are evidenced by the low interface trap density of as low as 2–4 × 1011 cm−2 eV−1 and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

Original languageEnglish
Article number224
JournalNanoscale Research Letters
Volume10
Issue number1
DOIs
StatePublished - 27 Dec 2015

Keywords

  • Gate-stacking heterostructure
  • Ge quantum dot
  • Self-aligned
  • SiGe channel

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