A unified model for partial-depletion and full-depletion SOI circuit designs: Using BSIMPD as a foundation

Pin Su*, Samuel K.H. Fung, Peter W. Wyatt, Hui Wan, Mansun Chan, Ali M. Niknejad, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

16 Scopus citations

Abstract

We present our approach to developing a unified SOI MOSFET model for circuit designs using state-of-the-art SOI technologies. Using BSIMPD as a foundation, we unify the PD and FD models by the concept of body-source built-in potential lowering. This unification is crucial due to the coexistence of PD/FD devices in a single chip as well as the coexistence of PD/FD behavior in a single device. The unified BSIMSOI model has been implemented in Berkeley SPICE3f4 and many commercial circuit simulators.

Original languageEnglish
Pages (from-to)241-244
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 19 Nov 2003
EventProceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: 21 Sep 200324 Sep 2003

Fingerprint Dive into the research topics of 'A unified model for partial-depletion and full-depletion SOI circuit designs: Using BSIMPD as a foundation'. Together they form a unique fingerprint.

Cite this