A unified 3D device simulation of random dopant, interface trap and work function fluctuations on high-κ/metal gate device

Yiming Li*, Hui Wen Cheng, Yung Yueh Chiu, Chun Yen Yiu, Hsin Wen Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

In this work, we for the first time estimate total fluctuation resulting from random dopants (RDs), interface trap (ITs) and work functions (WKs) using experimentally calibrated 3D device simulation on 16-nm-gate high-κ/metal gate devices. The total 3D simulated threshold voltage fluctuation (σV th), induced by the aforementioned random sources simultaneously, is 55.5 mV for NMOS; however, a statistical total sum of these fluctuations is 12.3% overestimation because independence assumption on random variables is invalid owing to strong interactions among RDs, ITs and WKs. Device's DC/AC and CMOS SRAM circuit fluctuations have similar observation. FinFET-based structure innovation possessing large fluctuation suppression (σV th = 30.2 mV; 45.6% reduction), compared with process efforts on planar one, is further discussed.

Original languageEnglish
Title of host publication2011 International Electron Devices Meeting, IEDM 2011
Pages5.5.1-5.5.4
DOIs
StatePublished - 2011
Event2011 IEEE International Electron Devices Meeting, IEDM 2011 - Washington, DC, United States
Duration: 5 Dec 20117 Dec 2011

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2011 IEEE International Electron Devices Meeting, IEDM 2011
CountryUnited States
CityWashington, DC
Period5/12/117/12/11

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