A Two-Directional BigData Sorting Architecture on FPGA

Bo Cheng C. Lai, Chun Yen Chen, Yi Da Hsin, Bo Yen Lin

Research output: Contribution to journalArticle

Abstract

Sorting is pivotal data analytics and becomes challenging with intensive computation on drastically growing data volume. Sorting on FPGA has shown superior throughput, but the limited in-system memory causes vast data transferring to/from external storage when handling a large dataset. We propose a two-directional sorting (2DSort) architecture which sorts data sequences on both horizontal and vertical directions. 2DSort significantly reduces the costly data transmission by tracking the data on FPGA and writes back the data to external storage when the final sorting position is determined. 2DSort shows average 38.5% runtime enhancement in comparison to state-of-the-art bigdata sorting engine on FPGA.

Original languageEnglish
JournalIEEE Computer Architecture Letters
DOIs
StateAccepted/In press - 1 Jan 2020

Keywords

  • B.2 Arithmetic and Logic Structures
  • B.5.1.c Data-path design
  • B.6.1.c Logic arrays
  • C.0.e System architectures
  • C.3.e Reconfigurable hardware
  • integration and modeling

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