A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW

Yi Zhang, Chia-Hung Chen, Tao He, Kazuki Sobue, Koichi Hamashita, Gabor C. Temes

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper presents a two-step incremental ADC (lADC) using extended counting. In the first step, the lADC is configured as a first-order ΔΣ loop with an input feedforward architecture. In the second step, a two-capacitor SAR-assisted extended counting technique enhances the accuracy. A single active integrator is shared in both steps. Fabricated in 0.18-μm CMOS process, the IADC achieves a peak SNR/SNDR/DR of 97.1/96.6/100.2 dB over a 1.2 kHz bandwidth, while dissipating 33.2 μW from a 1.5 V supply. This gives a Schreier FoM of 175.8 dB and Walden FoM of 0.25 pJ/conv.-step, both among the best values.

Original languageEnglish
Title of host publication38th Annual Custom Integrated Circuits Conference
Subtitle of host publicationA Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509051915
DOIs
StatePublished - 26 Jul 2017
Event38th Annual Custom Integrated Circuits Conference, CICC 2017 - Austin, United States
Duration: 30 Apr 20173 May 2017

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2017-April
ISSN (Print)0886-5930

Conference

Conference38th Annual Custom Integrated Circuits Conference, CICC 2017
CountryUnited States
CityAustin
Period30/04/173/05/17

Keywords

  • delta-sigma
  • extended counting
  • multi-step incremental ADC
  • SAR-assisted
  • two-capacitor

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