A tree-topology multiplexer for multiphase clock system

Hungwen Lu*, Chau-Chin Su, Chien-Nan Liu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

28 Scopus citations

Abstract

This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18-μ CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation.

Original languageAmerican English
Pages (from-to)124-131
Number of pages8
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume56
Issue number1
DOIs
StatePublished - 26 Feb 2009

Keywords

  • I/O
  • Multiplexer
  • MUX
  • Serdes
  • Serializer

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