A Theoretical Study of Gate/Drain Offset in LDD MOSFET's

J. Lee, K. Mayaram, Chen-Ming Hu

Research output: Contribution to journalArticle

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Abstract

A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor, indicating the effectiveness of an LDD design in reducing the peak channel field, is used to compared LDD structures with, without, and with partial gate/drain overlap. Plots showing the trade-off between, and the process-dependencies of the field reduction factor (FRF) and the series resistance are presented for the three cases. Structures with gate/drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate/drain offset can cause the rise of channel field and substrate current at large gate voltages. Good agreement with simulations is obtained.

Original languageEnglish
Pages (from-to)152-154
Number of pages3
JournalIEEE Electron Device Letters
Volume7
Issue number3
DOIs
StatePublished - 1 Jan 1986

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