A tableless approach for high-level power modeling using neural networks

Chih Yang Hsu*, Wen Tsan Hsieh, Chien-Nan Liu, Jing Yang Jou

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models have to increase their complexity in order to meet the accuracy requirement. In this paper, we propose a tableless power model for complex circuits that uses neural networks to learn the relationship between power dissipation and input/ output signal statistics. The complexity of our neural power model has almost no relationship with circuit size and number of inputs and outputs such that this power model can be kept very small even for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear characteristic of power distributions and the effects of both state-dependent leakage power and transition-dependent switching power. The experimental results have shown the accuracy and efficiency of our approach on benchmark circuits and one practical design for different test sequences with wide range of input distributions.

Original languageEnglish
Pages (from-to)71-90
Number of pages20
JournalJournal of Information Science and Engineering
Volume23
Issue number1
DOIs
StatePublished - 1 Jan 2007

Keywords

  • Low power design
  • Neural network
  • Power estimation
  • Power macromodel
  • RTL

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