A system architecture exploration on the configurable HW/SW co-design for H.264 video decoder

Guo An Jian*, Jui Chin Chu, Ting Yu Huang, Tao Cheng Chang, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

In this paper we focus on the design methodology to propose a design that is more flexible than ASIC solution and more efficient than the processor-based solution for H.264 video decoder. We explore the memory access bandwidth requirement and different software/hardware partitions so as to propose a configurable architecture adopting a DEM (Data Exchange Mechanism) controller to fit the best tradeoff between performance and cost when realizing H.264 video decoder for different applications. The proposed architecture can achieve more than three times acceleration in performance.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages2237-2240
Number of pages4
DOIs
StatePublished - 26 Oct 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
Duration: 24 May 200927 May 2009

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CountryTaiwan
CityTaipei
Period24/05/0927/05/09

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