A study of row-based area-array I/O design planning in concurrent chip-package design flow

Ren Jie Lee, Hung-Ming Chen

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this article, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile that combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring.

Original languageEnglish
Article number30
JournalACM Transactions on Design Automation of Electronic Systems
Issue number2
StatePublished - 1 Mar 2013


  • Area-array IC design
  • Chip-package feasibility study
  • Concurrent IC design flow
  • I/O-bump planning

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