A spread spectrum clock generator for SATA-II

Wei Ta Chen, Jen Chien Hsu, Hong Wen Lune, Chau-Chin Su

Research output: Contribution to journalConference articlepeer-review

26 Scopus citations

Abstract

In this paper, we proposed a spread spectrum clock generator (SSCG) for the Serial AT Attachment Generation 2 (SATA-II). We use a fractional-N PLL to accomplish the spread spectrum function. The SSCG integrates a conventional PLL, a digital 3rd order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 1.5 GHz, a 5000 ppm down spread with a triangular waveform frequency modulation of 33 KHz. The circuit has been simulated in 0.18 um CMOS technology. The non spread spectrum clocking has a jitter of 80ps and the peak amplitude reduction is 23.44 dBm in spread spectrum mode. The power dissipation from a 1.8V supply is 55 mW.

Original languageEnglish
Article number1465169
Pages (from-to)2643-2646
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 23 May 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

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