A spacer patterning technology for nanoscale CMOS

Yang Kyu Choi*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

192 Scopus citations

Abstract

A spacer patterning technology using a sacrificial layer and a Chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.

Original languageEnglish
Pages (from-to)436-441
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume49
Issue number3
DOIs
StatePublished - 1 Mar 2002

Keywords

  • Fin
  • FinFET
  • Nanoscale-CMOS
  • Spacer patterning process technology
  • Sub-10 nm pattern
  • Thin-body SOI
  • Ultrathin body (UTB) MOSFET

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