A software-hardware co-implementation of MPEG-4 Advanced Video Coding (AVC) decoder with block level pipelining

Shih Hao Wang*, Wen-Hsiao Peng, Yuwen He, Guan Yi Lin, Cheng Yi Lin, Shih Chien Chang, Chung Neng Wang, Tihao Chiang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

21 Scopus citations

Abstract

We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.

Original languageEnglish
Pages (from-to)93-110
Number of pages18
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume41
Issue number1
DOIs
StatePublished - 1 Aug 2005

Keywords

  • Advanced video coding (AVC)
  • H.264
  • Joint video team (JVT)
  • MB level pipelining
  • MPEG-4
  • Software-hardware co-implementation
  • Task partition

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