A single chip 2.5 Gbps CMOS burst mode optical receiver

Wei-Zen Chen*, Ruei Ming Gan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

This paper describes the design of a 2.5 Gbps burst-mode optical receiver in a 0.18 μm CMOS process. Integrating both transimpedance amplifier and post limiting amplifier in a single chip, the input sensitivity of the optical receiver is about -18 dBm, and the response time is less than 50 ns. The overall transimpedance gain is 98 dBΩ, and the -3 dB bandwidth is about 1.85 GHz. Operating under a single 1.8 V supply, this chip dissipates only 122 mW.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages120-121
Number of pages2
DOIs
StatePublished - 1 Dec 2006
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 15 Jun 200617 Jun 2006

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2006 Symposium on VLSI Circuits, VLSIC
CountryUnited States
CityHonolulu, HI
Period15/06/0617/06/06

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    Chen, W-Z., & Gan, R. M. (2006). A single chip 2.5 Gbps CMOS burst mode optical receiver. In 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 120-121). [1705339] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2006.1705339