A single-channel 10b 1GS/s ADC with 1-cycle latency using pipelined cascaded folding

Alireza Razzaghi*, Sai Wang Tam, Pejman Kalkhoran, Yu Wang, Chih Yi Kuan, Brian Nissim, Lan Duy Vu, Mau-Chung Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

A 10b 1GS/s ADC employing a single channel cascaded folding architecture is presented. Conversion speed of 1GS/s is attained by incorporating low-power distributed track-and-hold amplifiers after each folder. This ADC achieves a record 55.6dB peak SNDR and a 64dB peak SFDR and sustains a latency of one clock cycle. DNL and INL at 1GS/s sampling rate are measured 0.4LSB and 1.1LSB. Fabricated in a 0.35μm BiCMOS process, the ADC consumes 2W from a 3.5V supply.

Original languageEnglish
Title of host publication2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
Pages265-268
Number of pages4
DOIs
StatePublished - 30 Dec 2008
Event2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - Monterey, CA, United States
Duration: 13 Oct 200815 Oct 2008

Publication series

NameProceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting
ISSN (Print)1088-9299

Conference

Conference2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
CountryUnited States
CityMonterey, CA
Period13/10/0815/10/08

Keywords

  • ADC
  • Cascaded folding
  • Folding
  • Pipelined
  • SiGe BiCMOS process

Fingerprint Dive into the research topics of 'A single-channel 10b 1GS/s ADC with 1-cycle latency using pipelined cascaded folding'. Together they form a unique fingerprint.

Cite this