A Simple Punchthrough Model for Short-Channel MOSFET's

Fu Chieh Hsu; Richard S. Muller; Chen-Ming Hu

doi:10.1109/T-ED.1983.21298

A Simple Punchthrough Model for Short-Channel MOSFET's

Fu Chieh Hsu, Richard S. Muller, Chen-Ming Hu

International College of Semiconductor Technology

Research output: Contribution to journal › Article

19 Scopus citations

Abstract

Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometr cal effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 10¹⁴ and 6.6 × 10¹⁵ cm^-3 and channel lengths from 1 to 2 µm show good agreement with the theory.

Original language	English
Pages (from-to)	1354-1359
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	30
Issue number	10
DOIs	https://doi.org/10.1109/T-ED.1983.21298
State	Published - 1 Jan 1983

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Hsu, F. C., Muller, R. S., & Hu, C-M. (1983). A Simple Punchthrough Model for Short-Channel MOSFET's. IEEE Transactions on Electron Devices, 30(10), 1354-1359. https://doi.org/10.1109/T-ED.1983.21298

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