A Simple Punchthrough Model for Short-Channel MOSFET's

Fu Chieh Hsu; Richard S. Muller; Chen-Ming Hu

doi:10.1109/T-ED.1983.21298

A Simple Punchthrough Model for Short-Channel MOSFET's

Fu Chieh Hsu, Richard S. Muller, Chen-Ming Hu

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Abstract

Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometr cal effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 10¹⁴ and 6.6 × 10¹⁵ cm^-3 and channel lengths from 1 to 2 µm show good agreement with the theory.

Original language	English
Pages (from-to)	1354-1359
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	30
Issue number	10
DOIs	https://doi.org/10.1109/T-ED.1983.21298
State	Published - 1 Jan 1983

Access to Document

10.1109/T-ED.1983.21298

Fingerprint Dive into the research topics of 'A Simple Punchthrough Model for Short-Channel MOSFET's'. Together they form a unique fingerprint.

Cite this

@article{898aaff5f9f94a19bd7dfe1aa58f46e2,

title = "A Simple Punchthrough Model for Short-Channel MOSFET's",

abstract = "Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometr cal effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 1014 and 6.6 × 1015 cm-3 and channel lengths from 1 to 2 µm show good agreement with the theory.",

author = "Hsu, {Fu Chieh} and Muller, {Richard S.} and Chen-Ming Hu",

year = "1983",

month = jan,

day = "1",

doi = "10.1109/T-ED.1983.21298",

language = "English",

volume = "30",

pages = "1354--1359",

journal = "Ieee Transactions On Electron Devices",

issn = "0018-9383",

publisher = "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",

number = "10",

}

TY - JOUR

T1 - A Simple Punchthrough Model for Short-Channel MOSFET's

AU - Hsu, Fu Chieh

AU - Muller, Richard S.

AU - Hu, Chen-Ming

PY - 1983/1/1

Y1 - 1983/1/1

N2 - Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometr cal effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 1014 and 6.6 × 1015 cm-3 and channel lengths from 1 to 2 µm show good agreement with the theory.

AB - Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometr cal effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 1014 and 6.6 × 1015 cm-3 and channel lengths from 1 to 2 µm show good agreement with the theory.

UR - http://www.scopus.com/inward/record.url?scp=0020832242&partnerID=8YFLogxK

U2 - 10.1109/T-ED.1983.21298

DO - 10.1109/T-ED.1983.21298

M3 - Article

AN - SCOPUS:0020832242

VL - 30

SP - 1354

EP - 1359

JO - Ieee Transactions On Electron Devices

JF - Ieee Transactions On Electron Devices

SN - 0018-9383

IS - 10

ER -

A Simple Punchthrough Model for Short-Channel MOSFET's

Abstract

Access to Document

Other files and links

Cite this