A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique

Tzu I. Tsai*, Tien-Sheng Chao, Horng-Chih Lin, Tiao Yuan Huang, Yun Jie Wei

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We present a simple modified double-patterning (DP) technique with I-line stepper to define 23 nm nano-scale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate length down to 69 nm. With this approach, polycrystalline silicon (poly-Si) gate with line width down to 70 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography.

Original languageEnglish
Title of host publication4th IEEE International NanoElectronics Conference, INEC 2011
DOIs
StatePublished - 26 Sep 2011
Event4th IEEE International Nanoelectronics Conference, INEC 2011 - Tao-Yuan, Taiwan
Duration: 21 Jun 201124 Jun 2011

Publication series

NameProceedings - International NanoElectronics Conference, INEC
ISSN (Print)2159-3523

Conference

Conference4th IEEE International Nanoelectronics Conference, INEC 2011
CountryTaiwan
CityTao-Yuan
Period21/06/1124/06/11

Keywords

  • double pattern
  • MOSFETs
  • photoresist ashing

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