A SiGe-base PNP ECL circuit technology

D. L. Harame, J. H. Comfort, E. F. Crabbé, J. D. Cressler, J. D. Warnock, B. S. Meyerson, K. Y.J. Hsu, J. Cotte, C. L. Stanis, J. M.C. Stork, J. Y.C. Sun, D. A. Danncr, P. D. Agnello

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

In this work we present the first SiGe-base PNP ECL circuit results. The SiGe-base PNP circuit technology includes extended Ge-profile designs for low collector doping levels, a self-aligned transistor structure on deep and shallow trench isolation, and in-situ doped polysilicon emitter contacts. Circuit transistors are obtained wilh good Gummel characteristics, a current gain of 40, a low emitter resistance of 9 Ω, a pinched base sheet resistance of 9.5 kΩ/□, and a peak fT of 31 GHz at a VBC of 3 volts. The circuit transistors have low parasitics resulting in a peak fmax of 38 GHz at a VBC of 3 volts. An ECL ring oscillator delay of 44 ps was measured at 2.7 mW.

Original languageEnglish
Article number760245
Pages (from-to)61-62
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1993
Event1993 13th Symposium on VLSI Technology, VLSIT 1993 - Kyoto, Japan
Duration: 17 May 199319 May 1993

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