A side-wall transfer-transistor cell (SWATT Cell) for highly reliable multi-level NAND EEPROM's

Seiichi Aritome*, Yuji Takeuchi, Shinji Sato, Hiroshi Watanabe, Kazuhiro Shimizu, Gertjan Hemink, R. Shirota

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

A multi-level NAND Flash memory cell, using a new Side-WAH Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (Vth) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide Vth distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the Vth of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the Vu, distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.67 μm2 for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond.

Original languageEnglish
Pages (from-to)145-152
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume44
Issue number1
DOIs
StatePublished - 1 Jan 1997

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