A S/H interpolator for oversampling D/A converters

Chung-Yu Wu, Yie Yuan Shieu, Tsai Chung Yu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A new S/H interpolator for oversampling converters is proposed where the filter coefficients are linearly combined to form the symmetric terms. It is verified that the hardware implementation is efficient due to the decreased multiplier rate and compact digital circuits. These lead to the decrease of the coupled noise, so that the performance of the analog front-end circuits in oversampling D/A converters is not degraded.

Original languageEnglish
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages613-616
Number of pages4
ISBN (Electronic)0780305930
DOIs
StatePublished - 1 Jan 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: 10 May 199213 May 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2
ISSN (Print)0271-4310

Conference

Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
CountryUnited States
CitySan Diego
Period10/05/9213/05/92

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