A serial scan test vector compression methodology

Chau-Chin Su; Kychin Hwang

doi:10.1109/TEST.1993.470601

A serial scan test vector compression methodology

Chau-Chin Su^*, Kychin Hwang

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

36 Scopus citations

Abstract

This paper presents a serial scan test vector compression methodology for the test time reduction in a scan-based test environment. The reduction is achieved by the overlapping of two consecutive vectors. Hence, the order of test vectors determines the amount of reduction in time. Here, two test vector ordering algorithms, depth first greedy and coalesced simple orders algorithms, have been derived, implemented, and tested. Experimental results obtained are very close to estimations by statistical analysis.

Original language	English
Title of host publication	Proceedings of the International Test Conference
Editors	Anon
Publisher	Publ by IEEE
Pages	981-988
Number of pages	8
ISBN (Print)	0780314298
DOIs	https://doi.org/10.1109/TEST.1993.470601
State	Published - 1 Dec 1993
Event	Proceedings of the 24th IEEE International Test Conference - Baltimore, MD, USA Duration: 17 Oct 1993 → 21 Oct 1993

Publication series

Name	Proceedings of the International Test Conference

Conference

Conference	Proceedings of the 24th IEEE International Test Conference
City	Baltimore, MD, USA
Period	17/10/93 → 21/10/93

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10.1109/TEST.1993.470601

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title = "A serial scan test vector compression methodology",

abstract = "This paper presents a serial scan test vector compression methodology for the test time reduction in a scan-based test environment. The reduction is achieved by the overlapping of two consecutive vectors. Hence, the order of test vectors determines the amount of reduction in time. Here, two test vector ordering algorithms, depth first greedy and coalesced simple orders algorithms, have been derived, implemented, and tested. Experimental results obtained are very close to estimations by statistical analysis.",

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N2 - This paper presents a serial scan test vector compression methodology for the test time reduction in a scan-based test environment. The reduction is achieved by the overlapping of two consecutive vectors. Hence, the order of test vectors determines the amount of reduction in time. Here, two test vector ordering algorithms, depth first greedy and coalesced simple orders algorithms, have been derived, implemented, and tested. Experimental results obtained are very close to estimations by statistical analysis.

AB - This paper presents a serial scan test vector compression methodology for the test time reduction in a scan-based test environment. The reduction is achieved by the overlapping of two consecutive vectors. Hence, the order of test vectors determines the amount of reduction in time. Here, two test vector ordering algorithms, depth first greedy and coalesced simple orders algorithms, have been derived, implemented, and tested. Experimental results obtained are very close to estimations by statistical analysis.

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U2 - 10.1109/TEST.1993.470601

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M3 - Conference contribution

AN - SCOPUS:0027883903

SN - 0780314298

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BT - Proceedings of the International Test Conference

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Y2 - 17 October 1993 through 21 October 1993

ER -

A serial scan test vector compression methodology

Abstract

Publication series

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