A self calibrated ADC BIST methodology

Hung Kai Chen, Chih Hu Wang, Chau-Chin Su

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

26 Scopus citations

Abstract

A self calibrated BIST methodology is proposed to overcome the process variation of the BIST circuitry. Two test methods are proposed, one by statistical analysis and another by curve fitting. Test hardware is built by discrete components to emulate the ADC BIST circuitry. Experimental results verify the feasibility of the methodology.

Original languageEnglish
Title of host publicationProceedings - 20th IEEE VLSI Test Symposium, VTS 2002
PublisherIEEE Computer Society
Pages117-122
Number of pages6
ISBN (Electronic)0769515703
DOIs
StatePublished - 1 Jan 2002
Event20th IEEE VLSI Test Symposium, VTS 2002 - Monterey, United States
Duration: 28 Apr 20022 May 2002

Publication series

NameProceedings of the IEEE VLSI Test Symposium
Volume2002-January

Conference

Conference20th IEEE VLSI Test Symposium, VTS 2002
CountryUnited States
CityMonterey
Period28/04/022/05/02

Keywords

  • Automatic testing
  • Built-in self-test
  • Calibration
  • Circuit testing
  • Digital signal processing
  • Hardware
  • Harmonic analysis
  • Linearity
  • Quadrature amplitude modulation
  • Signal processing algorithms

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