A self-calibrate all-digital 3Gbps SATA driver design

Hsin Wen Wang; Hung Wen Lu; Chau-Chin Su

doi:10.1109/ASSCC.2005.251806

A self-calibrate all-digital 3Gbps SATA driver design

Hsin Wen Wang^*, Hung Wen Lu, Chau-Chin Su

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents an all digital Low Voltage Differential Signal (LVDS) driver for Serial-ATA (SATA-II) with simultaneous switching noise (SSN) reduction capability. An auto calibration mechanism is included to deal with the process and environmental variation. The chip is implemented using TSMC 0.18-μm 1P6M CMOS technology. The core area is 350×350 μ m ². The transmitter operates at 3 Gbps under a 1.8V power supply and consumes 11mW of power.

Original language	English
Title of host publication	2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Publisher	IEEE Computer Society
Pages	57-60
Number of pages	4
ISBN (Print)	0780391624, 9780780391628
DOIs	https://doi.org/10.1109/ASSCC.2005.251806
State	Published - 1 Nov 2005
Event	1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan Duration: 1 Nov 2005 → 3 Nov 2005

Publication series

Name	2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Conference

Conference	1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Country	Taiwan
City	Hsinchu
Period	1/11/05 → 3/11/05

Access to Document

10.1109/ASSCC.2005.251806

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title = "A self-calibrate all-digital 3Gbps SATA driver design",

abstract = "This paper presents an all digital Low Voltage Differential Signal (LVDS) driver for Serial-ATA (SATA-II) with simultaneous switching noise (SSN) reduction capability. An auto calibration mechanism is included to deal with the process and environmental variation. The chip is implemented using TSMC 0.18-μm 1P6M CMOS technology. The core area is 350×350 μ m 2. The transmitter operates at 3 Gbps under a 1.8V power supply and consumes 11mW of power.",

author = "Wang, {Hsin Wen} and Lu, {Hung Wen} and Chau-Chin Su",

year = "2005",

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doi = "10.1109/ASSCC.2005.251806",

language = "English",

isbn = "0780391624",

series = "2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005",

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address = "United States",

note = "null ; Conference date: 01-11-2005 Through 03-11-2005",

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Wang, HW, Lu, HW & Su, C-C 2005, A self-calibrate all-digital 3Gbps SATA driver design. in 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005., 4017530, 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, IEEE Computer Society, pp. 57-60, 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005, Hsinchu, Taiwan, 1/11/05. https://doi.org/10.1109/ASSCC.2005.251806

A self-calibrate all-digital 3Gbps SATA driver design. / Wang, Hsin Wen; Lu, Hung Wen; Su, Chau-Chin.

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. IEEE Computer Society, 2005. p. 57-60 4017530 (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents an all digital Low Voltage Differential Signal (LVDS) driver for Serial-ATA (SATA-II) with simultaneous switching noise (SSN) reduction capability. An auto calibration mechanism is included to deal with the process and environmental variation. The chip is implemented using TSMC 0.18-μm 1P6M CMOS technology. The core area is 350×350 μ m 2. The transmitter operates at 3 Gbps under a 1.8V power supply and consumes 11mW of power.

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A self-calibrate all-digital 3Gbps SATA driver design

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