A selective pattern-compression scheme for power and test-data reduction

Chia Yi Lin*, Hung-Ming Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supply the test patterns either through the compressed scan chain whose scanned values will be decoded to the original scan cells, or directly through the original scan chain using minimum transition filling method. Due to shorter length of a compressed scan chain, the potential switching activities and the required storage bits can be both reduced. Furthermore, the proposed scheme also supports multiple scan chains. The experimental results demonstrate that, with few hardware overhead, the proposed scheme can achieve significant improvement in shift-in power reduction and large amount of test data volume reduction.

Original languageEnglish
Title of host publication2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
Pages520-525
Number of pages6
DOIs
StatePublished - 1 Dec 2007
Event2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States
Duration: 4 Nov 20078 Nov 2007

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Conference

Conference2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
CountryUnited States
CitySan Jose, CA
Period4/11/078/11/07

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