A Scaled 0.25- μm Bipolar Technology Using Full e-Beam Lithography

John D. Cressler, James Warnock, Philip J. Coane, Kaolin N. Chiong, Mary E. Rothwell, Keith A. Jenkins, Joachim N. Burghartz, Edward J. Petrillo, Nickolas J. Mazzeo, Andrew C. Megdanis, Fritz J. Hohn, Michael G. Thomson, Jack Y.C. Sun, Denny D. Tang

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Abstract

The full leverage offered by electron-beam (e-beam) lithography has been exploited in a scaled 0.25- μm double-poly-silicon bipolar technology. Devices and circuits were fabricated using e-beam lithography for all mask levels with level-to-level overlays tighter than 0.06 μm. Ion implantation was used to form a sub-100-nm intrinsic base profile, and a novel in-situ doped polysilicon emitter process was used to minimize narrow emitter effects. Transistors with 0.25- μm emitter width have current gains above 80 and cutoff frequencies as high as 40 GHz. A record ECL gate delay of 20.8 ps at 4.82 mW has been measured together with a minimum power-delay product of 47 fJ (42.1 ps at 1.12 mW). These results demonstrate the feasibility and resultant performance leverage of aggressive scaling of conventional bipolar technologies.

Original languageEnglish
Pages (from-to)262-264
Number of pages3
JournalIEEE Electron Device Letters
Volume13
Issue number5
DOIs
StatePublished - May 1992

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    Cressler, J. D., Warnock, J., Coane, P. J., Chiong, K. N., Rothwell, M. E., Jenkins, K. A., Burghartz, J. N., Petrillo, E. J., Mazzeo, N. J., Megdanis, A. C., Hohn, F. J., Thomson, M. G., Sun, J. Y. C., & Tang, D. D. (1992). A Scaled 0.25- μm Bipolar Technology Using Full e-Beam Lithography. IEEE Electron Device Letters, 13(5), 262-264. https://doi.org/10.1109/55.145047