A Scaleable Technique for the Measurement of Intrinsic MOS Capacitance with Atto-Farad Resolution

Hiroshi Iwai*, John E. Oristian, James T. Walker, Robert W. Dutton

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

An on-chip capacitance measurement technique used for interline capacitances has been extended to MOS transistor capacitance measurements. The gate of the test transistor is connected to a reference capacitance made on the same chip. Small ac signals are applied to one of the transistor terminals successively. The magnitude of the ac voltages appearing on the gate node is measured indirectly. Cgd, Cgs and Cgb are calculated accurately from the measured ac voltage and the reference capacitance value. It was found that Cgd and Cgsare measured completely free of parasitic capacitances resulting from both the internal on-chip circuit and external wiring. The on-chip circuitry is simple and can easily be scaled down. These features insure this technique is the most suitable for the measurement of minimum-geometry transistors with atto-Farad-range resolution. It is shown that this technique has the ability to detect the capacitance difference which comes from the misalignment of source and drain metal connections. Measurements with this technique are used to first describe the short- and narrow-channel effects on MOS transistor capacitance.

Original languageEnglish
Pages (from-to)264-276
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume20
Issue number1
DOIs
StatePublished - Feb 1985

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