A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

Ke Wei Su*, Yi Ming Sheu, Chung Kai Lin, Sheng Jier Yang, Wen Jya Liang, Xuemei Xi, Chung Shi Chiang, Jaw Kang Her, Yu Tai Chia, Carlos H. Diaz, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

65 Scopus citations

Abstract

This paper demonstrates a new compact and scaleable model about the mechanical stress effect on MOS electrical performance induced by the shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

Original languageEnglish
Pages (from-to)245-248
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 19 Nov 2003
EventProceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: 21 Sep 200324 Sep 2003

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