This paper demonstrates a new compact and scaleable model about the mechanical stress effect on MOS electrical performance induced by the shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 19 Nov 2003|
|Event||Proceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States|
Duration: 21 Sep 2003 → 24 Sep 2003