A scalable digitalized buffer for gigabit I/O

Hung Wen Lu*, Chau-Chin Su, Chien-Nan Liu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

A serial input-output (I/O) composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the simultaneous switching noise simultaneously. With a TSMC 0.18-μm CMOS process, the I/O occupies an area of 0.014 mm2 and operates from 4 Gbps.9 V to 1.5 Gbps.1 V.

Original languageEnglish
Pages (from-to)1026-1030
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume55
Issue number10
DOIs
StatePublished - 1 Oct 2008

Keywords

  • Buffer
  • Input-output (I/O)
  • Simultaneous switching noise (SSN)

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