A scalable digitalized buffer for gigabit I/O

HungWen Lu*, Chau-Chin Su, Chien-Nan Liu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18μm CMOS process, the I/O occupies an area of 0.014mm2 and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.

Original languageAmerican English
Article number4672068
Pages (from-to)241-244
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 26 Dec 2008
EventIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
Duration: 21 Sep 200824 Sep 2008

Keywords

  • Buffer
  • I/O
  • SSN

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