A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18μm CMOS process, the I/O occupies an area of 0.014mm2 and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.
|Original language||American English|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 26 Dec 2008|
|Event||IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States|
Duration: 21 Sep 2008 → 24 Sep 2008