A room temperature 0.1 μm CMOS on SOI

G. G. Shahidi, C. Blair, K. Beyer, T. Bucelot, T. Buti, P. N. Chang, S. Chu, P. Coane, J. Comfort, B. Davari, R. Dennard, S. Furkay, H. Hovel, J. Johnson, D. Klaus, K. Kiewtniack, R. Logan, T. Lii, P. A. McFarland, N. MazzeoD. Moy, S. Neely, T. Ning, M. Rodriguez, D. Sadana, S. Stiffler, J. Sun, F. Swell, J. Warnock

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17 Scopus citations

Abstract

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick non-delpleted (0.1μm) SOI film, highly non-uniform channel doping and source-drain extension-HALO were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. Very high speeds were obtained: Unloaded delay was 20 psec, and fully loaded NAND (FI=FO=3, CL=0.3 pF) delay was 130 psec at supply of 1.8 V.

Original languageEnglish
Article number760228
Pages (from-to)27-28
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1993
Event1993 13th Symposium on VLSI Technology, VLSIT 1993 - Kyoto, Japan
Duration: 17 May 199319 May 1993

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