A robust ultra-low power asynchronous FIFO memory with self-adaptive power control

Mu Tien Chang*, Po-Tsang Huang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-VT 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply. Simulation results show that the proposed scheme has 16% to 94% power reduction over conventional designs. The proposed scheme is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 1.39uW power consumption at 5MHz reading frequency and 200kHz writing frequency.

Original languageEnglish
Title of host publication2008 IEEE International SOC Conference, SOCC
Pages175-178
Number of pages4
DOIs
StatePublished - 1 Dec 2008
Event2008 IEEE International SOC Conference, SOCC - Newport Beach, CA, United States
Duration: 17 Sep 200820 Sep 2008

Publication series

Name2008 IEEE International SOC Conference, SOCC

Conference

Conference2008 IEEE International SOC Conference, SOCC
CountryUnited States
CityNewport Beach, CA
Period17/09/0820/09/08

Fingerprint Dive into the research topics of 'A robust ultra-low power asynchronous FIFO memory with self-adaptive power control'. Together they form a unique fingerprint.

  • Cite this

    Chang, M. T., Huang, P-T., & Hwang, W. (2008). A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. In 2008 IEEE International SOC Conference, SOCC (pp. 175-178). [4641505] (2008 IEEE International SOC Conference, SOCC). https://doi.org/10.1109/SOCC.2008.4641505