TY - GEN
T1 - A robust ultra-low power asynchronous FIFO memory with self-adaptive power control
AU - Chang, Mu Tien
AU - Huang, Po-Tsang
AU - Hwang, Wei
PY - 2008/12/1
Y1 - 2008/12/1
N2 - First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-VT 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply. Simulation results show that the proposed scheme has 16% to 94% power reduction over conventional designs. The proposed scheme is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 1.39uW power consumption at 5MHz reading frequency and 200kHz writing frequency.
AB - First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-VT 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply. Simulation results show that the proposed scheme has 16% to 94% power reduction over conventional designs. The proposed scheme is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 1.39uW power consumption at 5MHz reading frequency and 200kHz writing frequency.
UR - http://www.scopus.com/inward/record.url?scp=67650272438&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2008.4641505
DO - 10.1109/SOCC.2008.4641505
M3 - Conference contribution
AN - SCOPUS:67650272438
SN - 9781424425969
T3 - 2008 IEEE International SOC Conference, SOCC
SP - 175
EP - 178
BT - 2008 IEEE International SOC Conference, SOCC
Y2 - 17 September 2008 through 20 September 2008
ER -