A robust ultra-low power asynchronous FIFO memory with self-adaptive power control

Mu Tien Chang; Po-Tsang Huang; Wei Hwang

doi:10.1109/SOCC.2008.4641505

A robust ultra-low power asynchronous FIFO memory with self-adaptive power control

Mu Tien Chang^*, Po-Tsang Huang, Wei Hwang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-VT 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply. Simulation results show that the proposed scheme has 16% to 94% power reduction over conventional designs. The proposed scheme is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 1.39uW power consumption at 5MHz reading frequency and 200kHz writing frequency.

Original language	English
Title of host publication	2008 IEEE International SOC Conference, SOCC
Pages	175-178
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2008.4641505
State	Published - 1 Dec 2008
Event	2008 IEEE International SOC Conference, SOCC - Newport Beach, CA, United States Duration: 17 Sep 2008 → 20 Sep 2008

Publication series

Name	2008 IEEE International SOC Conference, SOCC

Conference

Conference	2008 IEEE International SOC Conference, SOCC
Country	United States
City	Newport Beach, CA
Period	17/09/08 → 20/09/08

Access to Document

10.1109/SOCC.2008.4641505

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Cite this

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title = "A robust ultra-low power asynchronous FIFO memory with self-adaptive power control",

abstract = "First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-VT 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply. Simulation results show that the proposed scheme has 16% to 94% power reduction over conventional designs. The proposed scheme is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 1.39uW power consumption at 5MHz reading frequency and 200kHz writing frequency.",

author = "Chang, {Mu Tien} and Po-Tsang Huang and Wei Hwang",

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doi = "10.1109/SOCC.2008.4641505",

language = "English",

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Chang, MT, Huang, P-T & Hwang, W 2008, A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. in 2008 IEEE International SOC Conference, SOCC., 4641505, 2008 IEEE International SOC Conference, SOCC, pp. 175-178, 2008 IEEE International SOC Conference, SOCC, Newport Beach, CA, United States, 17/09/08. https://doi.org/10.1109/SOCC.2008.4641505

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AB - First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-VT 7T SRAM cell, the FIFO memory has improved stability under ultra-low voltage supply. Simulation results show that the proposed scheme has 16% to 94% power reduction over conventional designs. The proposed scheme is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 1.39uW power consumption at 5MHz reading frequency and 200kHz writing frequency.

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