A robust design for fully-silicided electrostatic discharge protection devices in sub-100 nm CMOS circuit era

Jam Wem Lee, Yi-Ming Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper we present a novel experimental methodology in studying a robust fully-silicided ESD protection device. The results demonstrate that the proposed floating body design is amenable to implement in sub-100 nm CMOS circuit. The design exhibits an excellent efficiency on both protection and chip area. This original technique is attractive to advanced CMOS circuit design; in particular for the consideration of ultra-thin gate-oxide reliability.

Original languageEnglish
Title of host publication2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings
PublisherIEEE Computer Society
Pages639-642
Number of pages4
ISBN (Electronic)0780379764
DOIs
StatePublished - 2003
Event2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - San Francisco, United States
Duration: 12 Aug 200314 Aug 2003

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
Volume2
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Conference

Conference2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003
CountryUnited States
CitySan Francisco
Period12/08/0314/08/03

Keywords

  • Biological system modeling
  • Circuit synthesis
  • CMOS technology
  • Electrostatic discharge
  • Laboratories
  • Nanoscale devices
  • Protection
  • Robustness
  • Very large scale integration
  • Voltage

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  • Cite this

    Lee, J. W., & Li, Y-M. (2003). A robust design for fully-silicided electrostatic discharge protection devices in sub-100 nm CMOS circuit era. In 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings (pp. 639-642). [1230993] (Proceedings of the IEEE Conference on Nanotechnology; Vol. 2). IEEE Computer Society. https://doi.org/10.1109/NANO.2003.1230993