A robust background calibration technique for switched-capacitor pipelined ADCs

Jen Lin Fan, Jieh-Tsorng Wu

Research output: Contribution to journalConference article

1 Scopus citations

Abstract

This work presents a robust background calibration scheme for switched-capacitor (SC) pipelined analog-to-digital converters. A SC multiplying digital-to-analog converter (MDAC) is usually linearized by high-gain capacitive feedback. Its conversion gain can be measured by splitting the input sampling capacitor and injecting a random sequence into the signal path. The magnitude of the random sequence can be extracted later in the digital domain. The use of input-dependent generation of the random sequence can eliminate the extra signal range requirement and also save calibration time. Furthermore, the use of random choppers to scramble signal can ensure that all necessary calibration data can be collected within a given time regardless of input conditions, resulting in a more robust ADC.

Original languageEnglish
Article number1464852
Pages (from-to)1374-1377
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

Fingerprint Dive into the research topics of 'A robust background calibration technique for switched-capacitor pipelined ADCs'. Together they form a unique fingerprint.

  • Cite this