A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

Bing-Fei Wu*, Chung Fu Lin

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

20 Scopus citations

Abstract

In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm2, and 150 MHz, respectively.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 14 Jul 2003
EventProceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 25 May 200328 May 2003

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