A reconfigurable MAC architecture implemented with mixed-Vt standard cell library

Li Rong Wang*, Yi Wei Chiu, Chia Lin Hu, Ming Hsien Tu, Shyh-Jye Jou, Chung Len Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, a 32-bit reconfigurable multiplication-accumulation architecture, which can execute flexibly one 32x32, two 16x16 or four 8x8 two's complement multiply-accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-Vt CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages3426-3429
Number of pages4
DOIs
StatePublished - 19 Sep 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: 18 May 200821 May 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period18/05/0821/05/08

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