The existing LDPC decoders are mostly based on the belief-propagation (BP) algorithms, due to good BER performances. However, they demand large chip areas. This paper proposes a high-throughput LDPC decoder based on the bit-flipping algorithms, for the (2048, 1723) RS-LDPC code adopted in the IEEE 802.3an standard. High decoding performances and low iteration numbers are achieved by introducing a strategy of flipping low-correlation bits and an additional syndrome vote scheme. As a result, the decoding performance is very close to the most popular BP-based min-sum algorithm (MSA) but with much lower computational complexity. Besides, the decoder achieves high hardware utilization with realtime processing capability. Synthesized with UMC 90nm process, the decoder chip area, throughput and average power dissipation are 1.42M gates, 16Gbps and 368mW, respectively, at 500MHz clock rate. Compared with existing BP-based designs, it has much smaller chip area and lower power dissipation, with comparable performances.