A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures

Jhin Bin Jiang*, Kuen Cheng Chiang, Jyh-Jiun Shann

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A coarse-grain reconfigurable architecture is an important technology for exploiting the parallelism of a program without compromise of the flexibility and has been adopted for high-performance embedded systems. However, the utilization of hardware resources may be limited by a large number of conditional executed operations. This paper represents a predicate-aware modulo scheduling which may map disjoint operations into the same processing element to reduce the requirements of hardware resources. Moreover, a weighted mapping decision algorithm has also been proposed to improve the execution performance for reconfigurable architecture. Our experimental results indicate that the initiation interval of a loop of the selected benchmarks may be reduced by 12% to 25.2% compared with a related work.

Original languageEnglish
Title of host publication7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings
Pages311-314
Number of pages4
DOIs
StatePublished - 31 Dec 2012
Event7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Karlsruhe, Germany
Duration: 20 Jun 201222 Jun 2012

Publication series

Name7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings

Conference

Conference7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012
CountryGermany
CityKarlsruhe
Period20/06/1222/06/12

Keywords

  • mode decision
  • modulo scheduling
  • predicated operation
  • reconfigurable architecture

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