Abstract
Negative Bias Temperature Instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (V-TH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change in rise time in a stressed ring oscillator. Simulations in IBM's 65nm PD/SOI CMOS technology demonstrate good linearity and an output sensitivity of 0.25mV/mV using the proposed scheme.
Original language | English |
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Title of host publication | IEEE International Symposium on Circuits and Systems (ISCAS 2009) |
Publisher | IEEE |
DOIs | |
State | Published - 2009 |
Keywords
- CMOS INVERTER; DELAY; MODEL