A Precise Negative Bias Temperature Instability Sensor using Slew-Rate Monitor Circuitry

Ghosh Amlan; Brown Richard B.; Rao Rahul M.; Ching-Te Chuang

doi:10.1109/ISCAS.2009.5117765

A Precise Negative Bias Temperature Instability Sensor using Slew-Rate Monitor Circuitry

Ghosh Amlan, Brown Richard B., Rao Rahul M., Ching-Te Chuang

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

Negative Bias Temperature Instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (V-TH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change in rise time in a stressed ring oscillator. Simulations in IBM's 65nm PD/SOI CMOS technology demonstrate good linearity and an output sensitivity of 0.25mV/mV using the proposed scheme.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems (ISCAS 2009)
Publisher	IEEE
DOIs	https://doi.org/10.1109/ISCAS.2009.5117765
State	Published - 2009

Keywords

CMOS INVERTER; DELAY; MODEL

Access to Document

10.1109/ISCAS.2009.5117765

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Cite this

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title = "A Precise Negative Bias Temperature Instability Sensor using Slew-Rate Monitor Circuitry",

abstract = "Negative Bias Temperature Instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (V-TH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change in rise time in a stressed ring oscillator. Simulations in IBM's 65nm PD/SOI CMOS technology demonstrate good linearity and an output sensitivity of 0.25mV/mV using the proposed scheme.",

keywords = "CMOS INVERTER; DELAY; MODEL",

author = "Ghosh Amlan and {Richard B.}, Brown and {Rahul M.}, Rao and Ching-Te Chuang",

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language = "English",

booktitle = "IEEE International Symposium on Circuits and Systems (ISCAS 2009)",

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Y1 - 2009

N2 - Negative Bias Temperature Instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (V-TH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change in rise time in a stressed ring oscillator. Simulations in IBM's 65nm PD/SOI CMOS technology demonstrate good linearity and an output sensitivity of 0.25mV/mV using the proposed scheme.

AB - Negative Bias Temperature Instability (NBTI) has become an important cause of degradation in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This paper proposes a scheme to detect PMOS threshold voltage (V-TH) degradation using on-chip slew-rate monitor circuitry. The degradation in the PMOS threshold voltage is determined with high resolution by sensing the change in rise time in a stressed ring oscillator. Simulations in IBM's 65nm PD/SOI CMOS technology demonstrate good linearity and an output sensitivity of 0.25mV/mV using the proposed scheme.

KW - CMOS INVERTER; DELAY; MODEL

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DO - 10.1109/ISCAS.2009.5117765

M3 - Conference contribution

BT - IEEE International Symposium on Circuits and Systems (ISCAS 2009)

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