A practical power model of AMBA system for high-level power analysis

Sung Che Li; Wei Ting Liao; Mu Shun Lee; Wen Tsan Hsieh; Chien-Nan Liu

doi:10.1109/VDAT.2009.5158166

A practical power model of AMBA system for high-level power analysis

Sung Che Li^*, Wei Ting Liao, Mu Shun Lee, Wen Tsan Hsieh, Chien-Nan Liu

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Nowadays, the communication architecture has become a major source of power consumption in complicated System-on-Chip (SoC) designs. In this paper, a practical cycle-accurate power model for on-chip communication architecture using AMBA system is proposed to help high-level power analysis. According to the distinct properties of each bus component, different methods are adopted to build accurate power models. In addition, the proposed power model can be integrated into RTL simulator easily, which allows performing the power analysis at high level. The experiment results have shown that the average error of the proposed power model is less than 5.14% and the simulation overhead is less than 8.7%.

Original language	English
Title of host publication	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages	347-350
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2009.5158166
State	Published - 1 Dec 2009
Event	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan Duration: 28 Apr 2009 → 30 Apr 2009

Publication series

Name	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country	Taiwan
City	Hsinchu
Period	28/04/09 → 30/04/09

Access to Document

10.1109/VDAT.2009.5158166

Fingerprint Dive into the research topics of 'A practical power model of AMBA system for high-level power analysis'. Together they form a unique fingerprint.

Cite this

Li, S. C., Liao, W. T., Lee, M. S., Hsieh, W. T., & Liu, C-N. (2009). A practical power model of AMBA system for high-level power analysis. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 (pp. 347-350). [5158166] (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09). https://doi.org/10.1109/VDAT.2009.5158166

@inproceedings{0cdaba7b78a0472eb99c84f34e2feeb8,

title = "A practical power model of AMBA system for high-level power analysis",

abstract = "Nowadays, the communication architecture has become a major source of power consumption in complicated System-on-Chip (SoC) designs. In this paper, a practical cycle-accurate power model for on-chip communication architecture using AMBA system is proposed to help high-level power analysis. According to the distinct properties of each bus component, different methods are adopted to build accurate power models. In addition, the proposed power model can be integrated into RTL simulator easily, which allows performing the power analysis at high level. The experiment results have shown that the average error of the proposed power model is less than 5.14% and the simulation overhead is less than 8.7%.",

author = "Li, {Sung Che} and Liao, {Wei Ting} and Lee, {Mu Shun} and Hsieh, {Wen Tsan} and Chien-Nan Liu",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/VDAT.2009.5158166",

language = "English",

isbn = "9781424427826",

series = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

pages = "347--350",

booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

note = "null ; Conference date: 28-04-2009 Through 30-04-2009",

}

Li, SC, Liao, WT, Lee, MS, Hsieh, WT & Liu, C-N 2009, A practical power model of AMBA system for high-level power analysis. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158166, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp. 347-350, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 28/04/09. https://doi.org/10.1109/VDAT.2009.5158166

A practical power model of AMBA system for high-level power analysis. / Li, Sung Che; Liao, Wei Ting; Lee, Mu Shun; Hsieh, Wen Tsan; Liu, Chien-Nan.

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 347-350 5158166 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A practical power model of AMBA system for high-level power analysis

AU - Li, Sung Che

AU - Liao, Wei Ting

AU - Lee, Mu Shun

AU - Hsieh, Wen Tsan

AU - Liu, Chien-Nan

PY - 2009/12/1

Y1 - 2009/12/1

N2 - Nowadays, the communication architecture has become a major source of power consumption in complicated System-on-Chip (SoC) designs. In this paper, a practical cycle-accurate power model for on-chip communication architecture using AMBA system is proposed to help high-level power analysis. According to the distinct properties of each bus component, different methods are adopted to build accurate power models. In addition, the proposed power model can be integrated into RTL simulator easily, which allows performing the power analysis at high level. The experiment results have shown that the average error of the proposed power model is less than 5.14% and the simulation overhead is less than 8.7%.

AB - Nowadays, the communication architecture has become a major source of power consumption in complicated System-on-Chip (SoC) designs. In this paper, a practical cycle-accurate power model for on-chip communication architecture using AMBA system is proposed to help high-level power analysis. According to the distinct properties of each bus component, different methods are adopted to build accurate power models. In addition, the proposed power model can be integrated into RTL simulator easily, which allows performing the power analysis at high level. The experiment results have shown that the average error of the proposed power model is less than 5.14% and the simulation overhead is less than 8.7%.

UR - http://www.scopus.com/inward/record.url?scp=77950644966&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2009.5158166

DO - 10.1109/VDAT.2009.5158166

M3 - Conference contribution

AN - SCOPUS:77950644966

SN - 9781424427826

T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

SP - 347

EP - 350

BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Y2 - 28 April 2009 through 30 April 2009

ER -