A power-aware me architecture using subsample algorithm

Hsien Wen Cheng*, Lan-Rong Dung

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

This paper presents a power-aware architecture driven by a novel content-based subsample algorithm which allows the architecture to work at different power consumption modes with acceptable and smooth quality degradation. The proposed algorithm first performs the edge extraction to generate a turn-off mask which is used to reduce the switch activities of processing elements (PEs) in the semi-systolic array. Since we introduce an adaptive control mechanism to set the threshold value of edge determination, based on the video content and the remaining capacity of battery pack, the reduction of the switch activities is rather stationary at a certain power consumption mode. As shown in simulation results, the architecture can dynamically operate at different power consumption modes with little quality degradation while the power overhead of edge extraction is under 0.8% comparing with the general subsample algorithm.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
DOIs
StatePublished - 7 Sep 2004
Event2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004

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