In this paper, a cost-effective and power-aware IP core design for computing the MPEG4 SA-DCT/IDCT is proposed. The proposed IP core has been developed based on the concept of programmable processors to provide the flexibility in dynamically configuring the hardware. The techniques exploited include adder-based distributed arithmetic, common sub-expression sharing, canonical signed digit (CSD) representation, and equipping interleaved RAM. The proposed IP core also possesses the feature of power-aware design flexibility allowing the trade-off of lower power consumption with less demand of data precision in developing its instruction library. This design has been realized based on a 035-μm CMOS technology and costs about 3100 gates with 32 words of RAM, which can achieve the real-time processing of the texture coding in MPEG4 SP@L3 and ACE@L2 codec system for the CIF video at 30 frames per second (fps).
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 7 Sep 2004|
|Event||2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: 23 May 2004 → 26 May 2004