A planar gate double beryllium implanted GaAs power MESFET for low voltage digital wireless communication application

Edward Yi Chang*, Chwan Shyan Fuh, Chin-Chun Meng, K. B. Wang, S. H. Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

An ion-implanted planar gate power MESFET for low voltage digital wireless communication system including DCS1800 (digital cellular system at 1800 MHz) and CDMA (code division multiple access) handset applications has been developed. The process for the device developed contains double Be implantation to reduce the surface and substrate defect trapping effects. The MESFET process developed has very little gate recess (less than 200 A), which greatly improves the uniformity and the yield of the wafer. The 1 μm × 20 mm MESFET manufactured using this planar gate technology exhibits an output power of 32.98 dBm and power added efficiency over 53% with gain of 11.2 dB when tested at 1.9 GHz under 3.6 V drain bias voltage and 80 mA quiescent drain current. The pinch off voltage of the 20 mm devices within a wafer is -2.81 V with a standard deviation of 120 mV. The device was also tested at 3.6 V and 1.9 GHz for CDMA application. Under the IS-95 CDMA modulation at 28 dBm output power, the device gain is 10.7 dB and the device has an adjacent channel power rejection (ACPR) of -29.5 dBc at 1.25 MHz offset frequency and -44.9 dBc at 2.25 MHz offset. The test data shows that the double Be implanted devices developed using the planar gate technology have very good linearity and efficiency and can be used for the low voltage DCS1800 and CDMA handset applications.

Original languageEnglish
Pages (from-to)1134-1138
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume47
Issue number6
DOIs
StatePublished - 1 Dec 2000

Keywords

  • Be ion implantation
  • CDM
  • Dcs1800, low voltage
  • MESFET
  • Planar gate

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