A phase-based single-bit Delta-Sigma ADC architecture

Yiqiao Lin*, De Wen Liao, Chung-Chih Hung, Mohammed Ismail

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed δσ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.

Original languageEnglish
Title of host publication2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
Pages406-409
Number of pages4
DOIs
StatePublished - 13 Sep 2011
Event2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011 - Bordeaux, France
Duration: 26 Jun 201129 Jun 2011

Publication series

Name2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011

Conference

Conference2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
CountryFrance
CityBordeaux
Period26/06/1129/06/11

Fingerprint Dive into the research topics of 'A phase-based single-bit Delta-Sigma ADC architecture'. Together they form a unique fingerprint.

  • Cite this

    Lin, Y., Liao, D. W., Hung, C-C., & Ismail, M. (2011). A phase-based single-bit Delta-Sigma ADC architecture. In 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011 (pp. 406-409). [5981256] (2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011). https://doi.org/10.1109/NEWCAS.2011.5981256